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Cantilever Probe Card

The evolutionary direction of display-driven chips (DDI) is high performance, low power, multi-channelization, and functional fusion

KI has been with the evolution of technology from the beginning of DDI to the present. We are preparing for the advent of the next generation of DDI while responding to Conventional Technology.

Application
DDI, SoC, Smart IC, CIS, ASIC
Features
Pitch : Fine pitch & Multi-DUT testing
Min. Pitch : DDI ( 12.5/25μm, 23μm) SoC (50μm)
Min. Pad Size : DDI (13X30μm) SoC (40X40μm)
Test Temp : -25℃ ~ 125℃
Test Frequency : < 6.5Gbpse
Delivery
TAT : 5 Weeks (5,000~6000 Pin) Depend on Pin Count